In semiconductor memory devices having a conventional nonvolatile memory cell, there are cases where a whole memory cell is covered by a cover film between the memory cell and an interlayer insulating film. Covering the whole memory cell by the cover film is for purposes of preventing spread of contamination to a device, and protecting the device from moisture or mechanical stress.
However, it is known that diffusion of hydrogen to a gate insulating film of a transistor influences reliability of the device (Non-Patent Documents 1 and 2). Hydrogen atoms are generally included in the interlayer insulating film, and the hydrogen atoms in the interlayer insulating film diffuse to the gate insulating film (tunnel insulating film), so that a threshold voltage Vt of the transistor varies, due to variation of hydrogen concentration in the gate insulating film. By the cover film lying between the memory cell and the interlayer insulating film, it is possible to suppress diffusion of the hydrogen atoms to the gate insulating film. The following technology is disclosed with regard to this type of cover film.
In Patent Document 1, a first layer in contact with a device surface is formed of silicon oxy-nitride deposited by a plasma-enhanced chemical vapor deposition (PECVD) process using silane as a reactant gas; a second layer is formed of silicon oxide provided by a chemical vapor deposition process using tetraethyl orthosilicate (TEOS) as a reactant gas; and a third layer is formed of silicon oxy-nitride deposited by a plasma-enhanced chemical vapor deposition (PECVD) process using silane as a reactant gas. It is disclosed that an advantage is obtained by using the silicon oxy-nitride is that concentration of free hydrogen inside the film is low. In addition, the silicon oxide of the second layer is disclosed to improve conformity. Furthermore, the silicon oxy-nitride of the third layer is disclosed to be a physical barrier against mechanical stress.
Patent Document 2 discloses a formulation having a surface oxide film in which, as a cover film, a first insulating film formed of a silicon nitride film (SiN) etc., is covered via a post-oxidized film on a device and a surface of the first insulating film has a surface oxide film formed by oxidizing. The first insulating film in which the surface oxide film is formed has a concentration gradient such that hydrogen concentration gradually becomes higher from a surface side thereof. In addition, it is disclosed that in the first insulating film (silicon nitride film) the hydrogen concentration in the film is less than or equal to approximately 1.6×1021 atom/cm3.
Patent Document 3 discloses a formulation in which, as a cover film, a post-oxidized film is formed by thermal oxidation on a device.    [Patent Document 1]
JP Patent Kokai Publication No. JP-A-11-233511    [Patent Document 2]
JP Patent Kokai Publication No. JP-P2000-311992A    [Patent Document 3]
JP Patent Kokai Publication No. JP-A-09-45799    [Non-Patent Document 1]
Ziyuan Liu and 7 others, Influence of Hydrogen Permeability of Liner Nitride Film on Program/Erase Endurance of Split-Gate Type Flash EEPROMs, International Reliability Physics Symposium (IRPS), US, IEEE, 2007, pp. 190-196.    [Non-Patent Document 2]
Susumu Shuto, and 4 others, Impact of Passivation Film Deposition and Post-Annealing on the Reliability of Flash Memories, International Reliability Physics Symposium (IRPS), US, IEEE, 1997, pp. 17-24.